1. Field of Invention
The present invention relates to a liquid crystal panel, and more particularly, to a liquid crystal panel capable of minimizing resistance difference between link lines and a liquid crystal display device having the same.
2. Description of Related Art
As the information-oriented society has developed, there are various demands for display apparatuses. To satisfy the demands, various flat display devices such as a liquid crystal display device (LCD, hereinafter referred to as ‘LCD’), a plasma display panel (PDP), and electro-luminescent display (ELD), and the like are developed and some of them have already been utilized as a display device in various equipments.
The liquid crystal display device is configured such that a data printed circuit board (PCB) for applying a data signal and a gate printed circuit board for applying a driving signal are coupled with a liquid crystal panel, in which an array substrate and a color filter substrate are bonded to each other, by means of a gate tape carrier package (TCP) and a data tape carrier package (TCP).
FIG. 1 is a plan view schematically illustrating a related liquid crystal display device.
As illustrated in FIG. 1, the related liquid crystal display device includes a liquid crystal panel 2, in which an array substrate having a plurality of gate lines and data lines intersecting each other is coupled with a color filter substrate having red, green and blue color filter layers by interposing a liquid crystal layer therebetween, and a gate (or scan) printed circuit board 22 (PCB) attached to a left side (or right side) of the liquid crystal panel 2 by interposing a gate (or scan) TCP 20 therebetween.
Moreover, a data (or source) printed circuit board (PCB) 32 is attached to the upper side (or the lower side) of the liquid crystal panel 2 by interposing the data (or source) TCP 30 therebetween.
The gate TCP 20 and the data TCP 30 electrically connect the gate PCB 22, the data PCB 32, and the liquid crystal panel 2 to each other to supply a signal supplied from the gate PCB 22 and the data PCB 32 to the liquid crystal panel 2.
The driving signal processed by the gate PCB 22 is supplied to the gate lines arranged in the liquid crystal panel 2 through the gate TCP 20, and similarly, a data signal processed by the data PCB 32 is supplied to the data lines arranged in the liquid crystal panel 2 through the data TCP 30.
A gate driver IC 21 is mounted on the gate TCP 20, and the gate driver IC 21 adjusts the driving signal supplied from the gate PCB 22 through a predetermined scheme to provide the adjusted driving signal to the gate lines arranged in the liquid crystal panel 2.
A data driver IC 31 is mounted on the data TCP 30, and the data driver IC 31 processes the data signal supplied from the data PCB 32 through a predetermined scheme to provide the processed driving signal to the date lines arranged in the liquid crystal panel 2.
FIG. 2 is a view illustrating a portion A shown in FIG. 1 in detail.
As illustrated in FIGS. 1 and 2, the data TCP 30 is provided with a plurality of output pads 25, in which the output pads 25 are connected to the data lines arranged in a display area B of the liquid crystal panel 2 by a plurality of link lines 35 corresponding to the output pads 25 one by one. In this case, the link lines 35 are formed in a non-display area A of the liquid crystal panel 2. In more detail, the output pads 25 are formed in a pad region C on the non-display area B of the liquid crystal panel 2, and the plurality of link lines 35 are formed on a link region D of the non-display area A of the liquid crystal panel 2.
The plurality of output pads 25 provided in the data TCP 30 are classified into first to third output pads 25a to 25c according to regions where the output pads 25 are located in the data TCP 30.
The second region of the data TCP 30, as illustrated in FIG. 2, indicates the central region among the regions where the output pads 25 are located in the data TCP 30. The first and third regions of the data TCP 30, as illustrated in FIG. 2, indicate the outer regions among the regions where the output pads 25 are located in the data TCP 30. More precisely, the first region is a left-side (or right-side) region to the second region and the third region is a right-side (or left-side) region to the second region. An output pad 25 located in the first region among the output pads 25 is referred to as a first output pad 25a, an output pad 25 located in the second region among the output pads 25 is referred to as a second output pad 25b, and an output pad 25 located in the third region in the data TCP 30 among the output pads 25 is referred to as a third output pad 25c. 
Similar to the plurality of output pads 25, from among the plurality of link lines 35, a link line electrically connected to the first output pact 25a is referred to as a first link line 35a, a link line electrically connected to the second output pad 25b is referred to as a second link line 35b, and a link line electrically connected to the third output pad 25c is referred to as a third link line 35c. 
In other words, the first link line 35a is electrically connected to the first output pad 25a, the second link line 351: is electrically connected to the second output pad 25b, and the third link line 35c is electrically connected to the third output pad 25c. 
Due to the region where the first to third output pads 25a to 25c are positioned, the length of the first link line 35a electrically connected to the first output pad 25a and the length of the third link line 35c electrically connected to the third output pad are longer than that of the second link line 35b electrically connected to the second output pad 25b formed in the second region.
Since the length of the first and third link lines 35a and 35c is longer than that of the second link line 35b, line resistance of the first and third link lines 35a and 35c is greater than that of the second link line 35b. For this reason, a resistance difference occurs among the first to third link lines 35a to 35c connected to the first to third output pads 25a to 25c, respectively. Due to the resistance difference between the first to third link lines 35a to 35c, the data signals supplied to the data lines corresponding to the first to third link lines 35a to 35c are distorted, so a problem such as degradation of image quality may occur.
In order to compensate for the resistance difference between the first to third link lines 35a to 35c, a process of forming a pattern to compensate for the resistance difference must be performed relative to the second link line 35b, causing increase of manufacturing costs.